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GATE ECE PYQ Mistake Book: Top Exam Traps

Deconstructed by Akshat • How to Eliminate MCQ Negative Marking • Tested on 15+ Years IIT Papers

Top 10 Most Frequent Traps Across GATE ECE Papers

Trap 1: Inductor Current / Capacitor Voltage Continuity with Impulses

The Trap: Blindly applying $i_L(0^+) = i_L(0^-)$ when an impulsive voltage source $\delta(t)$ is connected across an inductor.

The Reality: $i_L(0^+) - i_L(0^-) = \frac{1}{L}\int_{0^-}^{0^+} v_L(t) dt$. If $v_L(t) = A\delta(t)$, then $i_L$ jumps instantaneously by $\frac{A}{L}$! Continuity only holds when voltages and currents are finite.

Trap 2: Nyquist Rate for Product Signals vs Convolved Signals

The Trap: Assuming $x(t) = x_1(t) \cdot x_2(t)$ has the same bandwidth as $x_1(t) * x_2(t)$.

The Reality: Multiplication in time is convolution in frequency: $\omega_{max} = \omega_1 + \omega_2 \implies \omega_s = 2(\omega_1 + \omega_2)$. But convolution in time is multiplication in frequency: $\omega_{max} = \min(\omega_1, \omega_2) \implies \omega_s = 2\min(\omega_1, \omega_2)$.

Trap 3: Op-Amp Virtual Ground When Output Saturates

The Trap: Assuming $V_+ = V_-$ in every negative feedback Op-Amp circuit without checking if $V_{out}$ exceeds $V_{sat}$.

The Reality: Virtual short ($V_+ = V_-$) holds ONLY when the op-amp operates in its linear active region ($|V_{out}| \le V_{sat}$). If the calculated output exceeds supply rails, $V_{out}$ clamps at $\pm V_{sat}$ and the virtual ground breaks down!

Trap 4: Routh-Hurwitz Row of Zeros Auxiliary Equation Roots

The Trap: Forgetting to differentiate the auxiliary polynomial $A(s)$ with respect to $s$ to continue the Routh array, or missing that roots of $A(s)=0$ are roots of the original characteristic equation.

The Reality: A row of all zeros indicates roots symmetric about the origin (pure imaginary $\pm j\omega$, or quad pairs $\pm \sigma \pm j\omega$). Always form $A(s) = 0$ using the previous row, take $\frac{dA(s)}{ds}$, and solve $A(s)=0$ to find the marginal frequency $\omega_{osc}$.

Trap 5: Single-Sided vs Double-Sided Noise Spectral Density in Digital Comms

The Trap: Confusing single-sided noise PSD $N_0$ with double-sided noise PSD $N_0/2$.

The Reality: Noise power for filter bandwidth $B$: $P_N = N_0 B$ (using single-sided) or $\int_{-B}^{B} \frac{N_0}{2} df = N_0 B$. In bit error rate formulas $Q\left(\sqrt{\frac{2E_b}{N_0}}\right)$, $N_0$ is always the single-sided PSD ($k T$).

Trap 6: Waveguide Cutoff Condition vs Operating Frequency

The Trap: Using free-space wavelength $\lambda_0$ instead of guide wavelength $\lambda_g$ in transmission line sections of waveguides.

The Reality: Inside a waveguide, $\lambda_g = \frac{\lambda_0}{\sqrt{1-(f_c/f)^2}} > \lambda_0$. Always verify $f > f_c$ first; if $f < f_c$, the wave is evanescent (attenuates exponentially without propagating).

Trap 7: Conditional Probability Reduced Sample Space

The Trap: Misidentifying the denominator in Bayes' questions or forgetting to update the sample space.

The Reality: $P(A|B) = \frac{P(A \cap B)}{P(B)}$. Always write down the tree diagram and calculate $P(B)$ via total probability theorem before attempting the conditional step.

Trap 8: Symmetrical vs Reciprocal Two-Port Networks

The Trap: Assuming a network with equal input and output impedances is automatically reciprocal.

The Reality: Symmetry means $z_{11} = z_{22}$ or $A = D$. Reciprocity means $z_{12} = z_{21}$ or $AD - BC = 1$. A circuit with dependent sources can be symmetric without being reciprocal!

Trap 9: Slew Rate vs Bandwidth in High-Frequency Op-Amp Sinusoids

The Trap: Calculating distortion-free output solely from 3dB cutoff frequency without checking slew-rate distortion.

The Reality: An op-amp with high small-signal bandwidth can still produce distorted triangular waveforms if $2\pi f V_p > \text{Slew Rate}$. Maximum undistorted amplitude $V_{p,max} = \frac{\text{SR}}{2\pi f}$.

Trap 10: Counter Modulus with Asynchronous Clear Feedback

The Trap: Confusing the detected transient state with the counter's stable counting states.

The Reality: If NAND gate feeds active-low CLEAR at binary count 1010 (10 in decimal), the state 10 exists only for nanoseconds (propagation delay) before resetting to 0000. Hence the stable states are 0 through 9, making it a MOD-10 counter, NOT MOD-11!

How to Use This Mistake Book During Revision

💡 Strategy for Last 30 Days

1. Review these 10 core trap scenarios before solving any full-length CBT mock test.
2. When taking tests on the GATE ECE CBT Simulator, keep a physical notebook and note down every question where an unexpected trap tricked you.
3. For NAT questions: Double-check rounding requirements (e.g. "round off to two decimal places" vs "an integer").